1. Field of the Invention
The present invention relates to a semiconductor device having a semi-insulating isolation region, and a method for manufacturing the same.
2. Description of the Related Art
In a power semiconductor device such as a metal-oxide-semiconductor (MOS) field-effect transistor (FET) and a high power metal-insulator-semiconductor (MIS) FET, a vertical structure is suitable for a low on-state resistance and a high blocking voltage. For example, in an n-channel MOSFET, a current flows from a drain in a rear surface of a semiconductor substrate through a drift region of an n-type semiconductor layer into a source in a front surface of the semiconductor substrate. In order to achieve a high blocking voltage, the drift region is depleted. A resistance of the drift region primarily dominates in an on-state resistance of a power MOSFET. If a thickness of the drift region is reduced in order to decrease the on-state resistance, a blocking voltage is decreased.
In order to achieve a low on-state resistance and a high blocking voltage, a MOSFET having a super junction structure has been used. Generally, in a super junction structure, p-type element regions and n-type element regions are disposed adjacent to each other between source and drain regions. In an on-state of the MOSFET, a current flows through the n-type element regions as drift regions. In an off-state of the MOSFET, by depleting the adjacent p-type and n-type element regions, a high blocking voltage is achieved.
The p-type and n-type element regions in the super junction structure are formed in a semiconductor layer on a semiconductor substrate, for example, by doping impurities into sidewalls of deep trenches extending to the semiconductor substrate. Usually, the trenches are filled with dielectrics after formation of super junctions, so as to form isolation regions.
Alternatively, semi-insulating isolation regions have been proposed, in which a semi-insulating polycrystalline silicon (SIPOS) film is used instead of the dielectrics (see Japanese Patent Laid-Open No. 2002-217415). The SIPOS film is formed by oxidizing a deposited polycrystalline silicon (poly-Si). By burying the SIPOS film in trenches after formation of super junctions, high-resistance leakage current paths are provided between the source and the drain regions. As a result, a uniform field distribution is forcibly formed along a direction in which the SIPOS film is buried. Thus, an expected advantage is that a reduced surface field (RESURF) effect for the element regions is enhanced. Here, “RESURF” refers to a kind of junction termination which controls an electric field concentration in the vicinity of a p-n junction when a high voltage is applied.
However, it is difficult to control the oxygen (O) concentration included in the SIPOS film during the formation of the SIPOS film, which influences the resistance of the semi-insulating isolation regions. Thus, an O concentration distribution occurs in a depth direction in the SIPOS film. As a result, when planarizing the SIPOS film buried in the trenches, processing by wet etching and the like is difficult at a surface side of the SIPOS film having a high oxygen concentration. Moreover, a large film stress of the formed SIPOS film induces crystal defects in the drift region adjacent to the semi-insulating isolation region. Consequently, characteristics of the MOSFET are deteriorated.